For illustration, a static random access memory (SRAM) includes a pair of write bit lines WBL and WBLB. Further, a low and a high logical value are applied to corresponding write bit lines WBL and WBLB to be written to the memory cell. In various situations, a negative write bit line technique is used in which a voltage value lower than a value of supply voltage VSS is applied to bit line WBL, for example. In some approaches, a relatively large capacitor is used to generate the negative voltage for write bit line WBL, resulting in a large layout for the memory array having the memory cell.
Like reference symbols in the various drawings indicate like elements.